hola.
realice el siguiente código en vhdl en galaxy y lo simule, compilo y la simulación funcionó a la perfección (la primera vez), sin embargo al momento de armarlo no funcionó, prendió pero no hizo lo que tenia que hacer, a que crees que se deba?
library ieee;
use ieee.std_logic_1164.all;
entity deco is
port(a, b, c, d, ss1, ss2: in std_logic;
s, t, u, v: out std_logic);
-- ATTRIBUTE PIN_NUMBERS OF deco : ENTITY IS
-- "ss1:1 ss2:2 a:3 b:4 c:5 d:6 v:23 u:22 t:21 s:20";
end deco;
ARCHITECTURE arq_deco of deco is
begin
process(ss1, ss2, a, b, c, d)
begin
if (ss1='0' and ss2='0') then
s <= ((not a) and (not b));
t <= ((not a) and b);
u <= (a and (not b));
v <= ((not a) and (not b));
elsif(ss1='0' and ss2='1' and a='0') then
s <= b;
elsif(ss1='0' and ss2='1' and a='1') then
s <= c;
elsif(ss1='1' and ss2='0') then
s <= (((not a) and (not b) and c) or ((not a) and b and (not c)) or (a and (not b) and (not c)) or (a and b and c));
t <= (((not a) and b and c) or ( a and (not b) and c) or (a and b and (not c)) or (a and b and c));
elsif(ss1='1' and ss2='1') then
s <= not a;
t <= not b;
u <= not c;
v <= not d;
end if;
end process ;
end arq_deco;